The present invention relates to a computer system and more particularly to a method of calculating a processor utilization rate in a simultaneous multi-threading (hereinafter referred to as an SMT) processor and in an SMT processor environment.
Among very important approaches to improving performance of a processor and utilization of processor resources, there is a parallelization of instruction executions in the processor. Efforts have long been made to improve parallelism of instruction executions in one thread using a super scalar processor technology. In addition to this, recent years have seen a progressive improvement of thread-level parallelism being made based on a multi-threading technology that executes a plurality of threads on a single processor.
The multi-threading technologies that have come into wide use on processors include a simultaneous multi-threading (SMT). The SMT is a technique that makes one processor operate as a plurality of logidal processors by running it in two or more threads simultaneously. In the SMT capable of executing a plurality of threads simultaneously, these threads are called logical processors because the system takes these threads as a plurality of logical processors.
The SMT allows a plurality of logical processors to be active simultaneously with these logical processors contending for resources available in one processor. The SMT can improve an overall throughput of a plurality of software threads by letting a plurality of logical processors dynamically share the processor resources among them.
The SMT can also guarantee a performance equivalent to that of a single thread processor not only for a plurality, of software threads but also for a single software thread.
Take for example an SMT processor with two logical processors, such as a logical processor 0 and a logical processor 1. With this SMT processor there are two cases: one in which only one logical processor is active and one in which both of the two logical processors are active. The SMT processor offers two operation modes for these cases: a single task (ST) mode and a multitask (MT) mode. The ST mode is further broken down into an ST0 mode in which only the logical processor 0 is active and an ST1 mode in which only the logical processor 1 is active.
In the ST0 and ST1 modes the SMT allots all the processor resources to one logical processor and thus guarantees a performance equivalent to that of the single thread processor. In the MT mode, on the other hand, the processor resources are shared among the two logical processors. In the MT mode, although the performance depends on the kind of software running on the logical processors, these logical processors achieve a performance of about 60% that of the single thread processor individually and, when combined, about 120%.
When a logical processor executes a HALT instruction, the SMT processor transits from the MT mode to the ST0 mode or ST1 mode, depending on which of the logical processors has executed the instruction. If the remaining active logical processor also executes the HALT instruction, the SMT processor enters a power save mode. When, during the ST0 mode or ST1 mode, a HALT exit command in the form of, for example, an external interrupt is issued to a logical processor that is at rest, the SMT processor moves to the MT mode.
A processor utilization rate needs to be measured to monitor in real time the utilization state of the computer system or to control the allocation of the processor resources according to a load.
In single threading processors, the measurement of individual processors' processor utilization rate is relatively simple. Time spent in processing can be used as is. Dividing the time that the processor has been running by an elapsed time results in the processor utilization rate for that processor being determined. Even if a plurality of software processes or threads are being executed on one processor, they are not executed simultaneously but sequentially. So, the processor utilization rate for the software processes or threads can be determined similarly with ease.
In the SMT processors, on the other hand, since a plurality of logical processors run simultaneously in one processor, the processor utilization by each logical processor cannot be determined correctly by the simple measurement of time alone. So, in the SMT processor environment it is necessary to use a method that is different from the one used on the single threading processors and which calculates an SMT-aware processor utilization by each logical processor and a processor utilization by the SMT processor as a whole.
U.S. Pat. No. 7,657,893 describes a method for measuring the processor utilization for each logical processor in an SMT processor. U.S. Pat. No. 7,555,753 describes a method for calculating the processor utilization with respect to an entire SMT processor resource in the SMT processor environment.